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(R)
TDA7311
SERIAL BUS CONTROLLED AUDIO PROCESSOR
INPUT MULTIPLEXER - TWO STEREO DIFFERENTIAL INPUTS - TWO STEREO SINGLE ENDED INPUTS - ONE MONO DIFFERENTIAL INPUT INPUT AND OUTPUT FOR EXTERNAL EQUALIZER OR NOISE REDUCTION SYSTEM VOLUME CONTROL IN 1.25dB STEPS TREBLE AND BASS CONTROL FOUR SPEAKER ATTENUATORS: - 4 INDEPENDENT SPEAKERS CONTROL IN 1.25dB STEPS FOR BALANCE AND FADER FACILITIES - INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SPI COMPATIBLE SERIAL BUS DESCRIPTION The TDA7311 is a volume, tone (bass and treble) and fader (front/rear) processor for high quality audio applications in car radio and Hi-Fi systems. PINS CONNECTION (Top view)
DIP40
ORDERING NUMBER: TDA7311
Control is accomplished by serial bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS technology, low distortion, low noise and DC stepping are obtained.
July 1999
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TDA7311
TEST CIRCUIT
THERMAL DATA
Symbol R th j-pins Thermal Resistance Junction-pins Description max DIP40 85 Unit C/W
ABSOLUTE MAXIMUM RATINGS
Symbol VS Top Tstg Operating Supply Voltage Operating Temperature Range Storage Temperature Range Parameter Value 11.2 -40 to 85 -55 to +150 Unit V C C
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Volume Control Treble Control BR SS 1.25dB step 2dB step 1.25dB step -78.75 -14 -20 -38.75 92 Parameter Min. 8 2.3 0.01 106 95 +11.25 +14 +20 0 Typ. 10 Max. 11 Unit V Vrms % dB dB dB dB dB dB dB
Bass Control 2dB step Fader and Balance Control Mute Attenuation
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BLOCK DIAGRAM
IN4
9 10 11 12 13 14
IN3 SPKR ATT 15 MUTE
8
4
DIFF STEREO 1
LEFT INPUTS
5
OUT LEFT FRONT
7 VOL BASS TREBLE
SPKR ATT 16 MUTE OUT LEFT REAR
DIFF STEREO 2
6
38 SECMUTE SPI BUS DECODER + LATCHES SECMUTE
20 19 18 21
CL DA CE DIG GND
DIFF MONO
3
34 SPKR ATT VOL BASS TREBLE MUTE 26 OUT RIGHT FRONT
DIFF STEREO 2
35
37 SPKR ATT
RIGHT INPUTS
DIFF STEREO 1
36
25 MUTE
OUT RIGHT REAR
IN3
33 SUPPLY 31 30 29 28 27 1 40 2
IN4
32
D94AU178
VCC
AN-GND
CREF
TDA7311
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TDA7311
ELECTRICAL CHARACTERISTICS (Tamb = 25C, VCC = 10V, RL = 10K, RG = 600, GV=0dB, f = 1KHz unless otherwise specified) (refer to the test circuit)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
VS IS SVR Supply Voltage Supply Current Ripple Rejection 55 8 10 15 80 11 20 V mA dB
INPUT SELECTORS
R II V CL CMRR INS RL CL RO GIN Input Resistance Clipping Level Common Mode Rejection Input Separation (2) Output Load resistance Output Load capacitance Output Impedance Input Gain Single Ended Inputs differential Inputs -1 -7 15 0 -6 Single Ended inputs Differential Inputs Single Ended Inputs Differential Inputs Differential Inputs 70 2 1 50 1 -5 30 10 2.3 4.6 50 20 2.8 5.6 65 90 70 K K Vrms Vrms dB dB K nF dB dB
VOLUME CONTROL
R IN GR ASTEP EA ET VDC Vimax. Input Resistance Control Range Step Resolution Attenuation Set Error Tracking Error DC Steps Max. Input Voltage adjacent attenuation steps From 0dB to AVmax 2.3 0 1 2.8 AV = +11.25 to -20dB AV = -20 to -60dB -1.25 -3 Max. Attenuation Max. Gain 15 30 - 75 +11.25 1.25 0 1.25 2 2 3.0 10.0 k dB dB dB dB dB dB mV mV Vrms
SPEAKER ATTENUATORS
AR Astep EA VDC Control Range Step Resolution Attenuation set error DC Steps adjacent att. steps from 0 to mute 0 1 37.5 1.25 1.5 dB dB dB mV mV
BASS CONTROL (1)
Control Range Step Resolution Attenuation / Gain set error -2.0 +20 2 2.0 dB dB dB
TREBLE CONTROL (1)
Control Range Step Resolution Attenuation / Gain set error -1.0 +14 2.0 0 1.0 dB dB dB
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TDA7311
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUTS
Output Voltage Output Load Resistance Output Load Capacitance Output resistance DC Voltage Level 4.6 25 5.0 d = 0.3% 2.3 2 10 75 5.4 2.8 Vrms K nF V
GENERAL
e NO Output Noise BW = 20-20KHz, flat output muted all gains = 0dB Single Ended all gains = 0dB Diff. Inputs all gains = 0dB; VO = 1Vrms Single Ended Differential Inputs VIN = 1Vrms 70 AV = 0 to -20dB AV = -20 to -60 dB AV = 0dB to 11.25dB Mute Condition (3) 80 4 5 10 106 100 0.01 95 0 0 0 90 1 2 1 V V V dB dB % dB dB dB dB dB
15 30
S/N
Signal to Noise Ratio
d Sc
Distortion Channel Separation left/right Total Tracking error
Output Attenuation
BUS INPUTS
V IL VIH
Notes: (1) Bass and Treble response see attached diagram (fig.17). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network (2) The selected input is grounded thru the 2.2F capacitor. (3) Condition obtained programming: mute on speaker attenuators (1X111111) followed by selection of SECMUTE (1XXXX111).
Input Low Voltage Input High Voltage 3
1
V V
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TDA7311
APPLICATION INFORMATION SERIAL BUS INTERFACE The serial bus interface is compatible to SPI bus systems. During the LOW state of the chip enable signal (CE) the data on pin DA are clocked into the shift register at the LOW to HIGH transition of the clock signal CL. At the LOW to HIGH transition of the CE signal the content of the internal shift register is stored into the addressed latches. Figure 1: BUS Timing The transmission is separated into bytes with 8 bit according to the data specification of the audioprocessor. After every byte a positive slope of the CE signal has to be generated in order to store the data byte. A special clock counter enables the latch of the data byte only, if exactly 8 clocks were present during the LOW state of the CE signal. This results in a high immunity against spikes on the clock line and avoids a storage of wrong databytes.
Nr. Clock Frequency 1 2 3 4 5 6 7 8 9 CE Lead time Clock High Time Clock Low Time Data Hold Time Data Setup Time Clock Setup Time CE lagtime Clock Hold Time CE High TIme
Parameter
Min. 4 2 2 1.8 1.8 0 0 6 6
Max. 250
Units KHz s s s s s s s s s
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TDA7311
STATUS AFTER POWER-ON RESET
Volume Speaker Audio Switch Bass Treble -78.75dB Mute Mute -20dB -14dB
SOFTWARE SPECIFICATION Data Bytes FIRST BYTE
MSB 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X LSB X X X X X X X X X Function VOL ATTENUATION VOL GAIN BASS TREBLE ATT RF (speaker) ATT RR (speaker) ATT LF (speaker) ATT LR (speaker) AUDIO SWITCH
SECOND BYTE VOLUME ATTENUATION
MSB 1 X B2 B1 B0 A2 0 0 0 0 1 1 1 1 1 X B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A1 0 0 1 1 0 0 1 1 LSB A0 0 1 0 1 0 1 0 1 Volume 1.25dB Steps 0 -1.25 -2.5 -3.75 -5.00 -6.25 -7.50 -8.75 Volume 10dB Steps 0 -10 -20 -30 -40 -50 -60 -70
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TDA7311
SOFTWARE SPECIFICATION (continued) VOLUME GAIN
MSB 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 LSB 0 1 0 1 0 1 0 1 0 1 1.25dB STEPS 0.00 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10.00 11.25
SPEAKER ATTENUATION
MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 1.25dB STEPS 0 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 -8.75 10dB STEPS 0 -10 -20 -30 MUTE
AUDIO SWITCH
MSB 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 0 0 1 1 0 1 LSB 0 1 0 1 0 1 INPUT MONO DIFF1 DIFF2 IN3 IN4 SECMUTE
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TDA7311
SOFTWARE SPECIFICATION (continued) TREBLE
MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 LSB 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 2dB STEPS 14 12 10 8 6 4 2 0 -0 -2 -4 -6 -8 -10 -12 -14
BASS
MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 LSB 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 2dB STEPS -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 18 20
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TDA7311
DIM. MIN a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 48.26 14.1 0.175 0.23 1.27 52.58 16.68 0.598 0.100 1.900 0.555 mm TYP 0.63 0.45 0.31 0.009 0.050 2.070 0.657 MAX MIN inch TYP 0.025 0.018 0.012 MAX
OUTLINE AND MECHANICAL DATA
DIP40
0.130
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TDA7311
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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